Tuesday, August 18, 2026
Ryan Scherbarth (nvidia) joined the channel
David Ozog joined the channel
Jiaqi Lou joined the channel
bsahu joined the channel
Fabian joined the channel
Francois Labonte joined the channel
Daud Arslan joined the channel
Shahbozbek Hakimov joined the channel
Tong Xu joined the channel
myoung-gyun.suh joined the channel
xi.chen joined the channel
Mahfuz joined the channel
Varun Chotalia joined the channel
pierre-louis.benard joined the channel
Matthew Fricke joined the channel
Advm joined the channel
ahmadrazarehman033 joined the channel
Howard Wang joined the channel
rashid-ahmed.kukkady joined the channel
Kulika Weizman joined the channel
Thursday, August 20, 2026
R
Hello & Good Morning, This is Ravi Mahatme from Marvell.
J
Please ask Ravi to share slides
S
we will inform Ravi
š 1
L
What about software support for using memory appliance?
1 reply
R
This works as a standard CXL driver. For integration with AI libraries, this will need integration with AI libraries like vLLM, LMCache. This can be done by customers or we have a team looking into it as well
L
Does PFMA support 2 tier scale up?
1 reply
R
Yes it has the capability to be tiered to increase the radix but it adds a hop
M
What company is building your shuffle or is this designed and built in house?
1 reply
R
This is designed in house by our photoncis team but we work with external vendors to have this manufactured
J
Do you have plans to increase the fan-out connectivity from this appliance to more than 16, e.g. by introducing a switching fabric?
1 reply
R
There are multiple ways we can increase the radix
1. Add more appliances as a 2nd tier but ths will add a hop
2. Add an OCS as the 2nd tier, this probably is the lowest latency solution
3. Build a 2nd generation appliance which has a higher radix.
What we have right now is our Gen1 appliance
J
Very interesting design. Thank you for the presentation. What is the utility of two HBM3e memories (>2 TB/s) given the remote memory access bandwidth into/out of the device seems to be 16*224Gb/s=~ 448 GB/s? Would not one HBM3e suffice as a fast "L4 cache" in front of the fully populated dimms? (What is the approx. total DRAM bandwidth to the DDR DIMMs?)
1 reply
R
With 2 HBM you can have lot more transactions in flight as each HBM has 32 virtual channels. The max value of this appliance is when you integrate with the PF-chiplet as it gives you full bandwidth
For DRAM bandwidth, these run at 5200Mbps and 2 DPC
L
Why not to use PFMA as scale up switch?
1 reply
R
It is not a full featured scale-up switch with all advanced features a typical switch has but it can provide basic scale-up switch functionality if required.
A
Can we please get the slides?
2 replies
R
Yes, please email me : <mailto:rmahatme@marvell.com|rmahatme@marvell.com>
M
What is the energy efficiency for Marvell photonic fabric in terms of pJ/bit?
4 replies
L
It is available on Celestial ai presentation
š 1
M
Where can I find out about this presentation?
Can you share it with me? Thanks
L
Watch hot chip presentation
L
Or message me on LinkedIn. I can share
š 1
L
What are supply chain challenges for building PFMA?
3 replies
R
This is a multi-disciplinary device incorporating advanced 5nm ASICs, optical interposers, HBM , shuffles, lasers etc, so needs a well oiled supply chain.
We have been working on it since Celestial AI times and now after joining Marvell, we can leverage Marvell's supply chain expertise and resources
L
When product will be ready?
R
Please email me at <mailto:rmahatme@marvell.com|rmahatme@marvell.com>
S
@rmahatme363 sorry for mistagging, see questions above
N
That was a fascinating talk thank you Ravi, I am not sure if I am wording this well but at what point can you start see kv cache as behaving like a local memory, is there some kind of latency budget you see for it?
1 reply
R
I think we are already seeing KVCache change from being stateless (for basic chat applications) to being stateful (for agentic AI) , so I think there is going to be a requirement for both - lots of fast local memory ( for hot & warm KVCache) and for long term storage ( to store stateful KVCache)
š 1š 1
A
Since Marvell also has the newer Structera S CXL switches, have you compared the appliance against a current CXL 3.x pool? The paper comparison seems to use an older CXL 2.0 switched setup, so Iām curious how much of the latency gap remains with the latest electrical baseline.
1 reply
R
Our perf team is working on this.