Tuesday, August 18, 2026
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Thursday, August 20, 2026
S
ask questions to Alex @aa
A
Has Napatech tried to implement MRC on their NICs?
2 replies
A
No Napatech has no a NIC with MRC implemented today
C
@aa If an ASIC development track is a multi-year process, how should we think about Napatech's turnaround time to support a customer's everchanging need?
1 reply
A
We work with several customers and are able to make very fast turn-arounds when needed
L
Who uses your NICs for AI inference? I do not mean inference for trading .
2 replies
A
D-Matrix is one AI inference customer
L
@aa , so, d-Matrix does not use its own NIC (jestStream)
L
What are the disadvantages of FPGA-based NIC rather than ASIC-based?
1 reply
A
Price is probably the most important
C
@aa What are some of the key feataures you are currently looking to help customer support ahead of ASIC timelines when it comes to AI inference?
1 reply
A
I cannot reveal details on customer projects - but you are welcome to contact us and we can discuss more details
L
Has Napatech any specific feature or logic for scale across? Do you target scale up?
2 replies
A
We are working with AI customers on both scale-out and scale-across but are open to solving other use cases as well
L
Who is your scale across customer? Do you have specific solution for scale across like special congestion control?
L
What is maximum line rate supported by Napatech NICs? I think programmability comes with reducing packet per second.
1 reply
A
We can support any port speed that is supported by FPGA vendors - today we get to 400Gbps
R
How do you decide which networking functions should stay programmable versus eventually being hardened into an ASIC?
1 reply
A
For FPGA based solutions everything is programmable, if building ASIC based programmable infrastructure you will have to choose wisely as you do not want hardened functionality that is not needed when the ASIC is ready - but to answer that we will need more time and information about the use case
C
@aa we see that many AI inference vendors are starting to deploy heterogenous disag of prefill and decode across different GPU/XPUs across a single workload. Can you help us understand if the FPGA-based NICs can help solv the interconnet between (e.g.) an Nvidia domain and an AMD, Cerebrea, or other domain?
1 reply
A
If a "solution" exists it can be done in a FPGA based solution and much faster than an ASIC based one. And I think this is a very interesting use case and with a time window before an ASIC based solution is available - the good thing is that we can evolve ad improve a chosen solution over time through updates
T
@aa What kinds of interfaces do you use to connect the FPGA to the rest of the system? Ethernet, PCIe, fiber optics or other chip-to-chip interfaces? Thanks!
1 reply
A
We typically use PCI on the host side and ethernet on the network side - and that is like fixed due to the current hardware that we have - It can be changed but requires a hardware re-spin - but still much faster than ASICs
S
please tag @aa in your questions, thanks!
I
@aa what protocols does Napatech support today to help scale-up and scale-out inter node and intra node communication between the many different xPUs out there?
1 reply
A
We are new in the AI business and are mainly working with selected customers on their needs but we are very open to discuss any requirements you may have and then we can tell what we can deliver today
C
@aa Today's AI-fabric NICs in this space are largely 400G-class. As scale-up and scale-out fabrics move toward 800G per endpoint, what does your roadmap look like at that port speed - and which FPGA platform generation does that depend on?"
2 replies
A
But please contact our sales to get the latest roadmap for more precise dates
A
Today we support up to 400Gbps - but 800Gbps and beyond is coming based on the next generation FPGAs but for more precise dates please contact sales
A
@aa You mentioned a new algorithm can move from a paper into production within a quarter. What usually takes longest in that cycle, for instance RTL or HLS work, place-and-route, verification, or fleet qualification and is there a concrete AI-fabric feature you’ve shipped that way?
1 reply
A
Depending on the algorithm it may or may not require changes to the RTL - sometimes software changes is enough. But even RTL changes can be done quite fast and here I think the architecture of a new feature is the most important and then off course RTL work and verification. I cannot comment on customer features here but please take contact through sales for more detailed information
C
@aa You mentioned PCIe on the host side and ethernet on the network side. Amid all the talk about optical for scale up/out, can you or are you planning to support optical on either side?
1 reply
A
We are following the development here as we may be depending on FPGAs supporting this - but other alternatives are possible depending on the use case
Friday, August 21, 2026
C
@aa in hetero disagg, is it viable to build an FPGA-based solution that can act as a bridge/translator between scale-up fabrics like NVLink, xGMI and UALink? Thinking an image that can talk all "languages" without having to reload different images