2026-d2-1040-lightning-talks-session-msa

Archived conversation · Aug 13, 2026 8:41 PM – Aug 21, 2026 2:41 PM · 53 messages
Thursday, August 13, 2026

Ryan Scherbarth (nvidia) joined the channel
Friday, August 14, 2026

Redfire joined the channel
Sunday, August 16, 2026

Gunethra joined the channel
Monday, August 17, 2026

alnonecat joined the channel
Tuesday, August 18, 2026

Steve Glaser (NVIDIA) joined the channel
Dr ABANDA EVA Pierre Robert joined the channel
Allen Baum joined the channel
Taylor Groves joined the channel
David Ozog joined the channel
Sayan Ghosh joined the channel
Pepper Marts joined the channel
Dan Pitt joined the channel
Marc Cohn joined the channel
Matthew Fricke joined the channel
Rohit Zambre joined the channel
Yiltan Temucin joined the channel
aysebilgehan_baspinar joined the channel
Kapil Shrikhande joined the channel
Subhadeep Bhattacharya joined the channel
Ryan Scherbarth (nvidia) renamed the channel from "2026-d2-1040-msa-lightning-talks" to "2026-d2-1040-lightning-talks-msa"
Ryan Scherbarth (nvidia) renamed the channel from "2026-d2-1040-lightning-talks-msa" to "2026-d2-1040-lightning-talks-session-msa"
Thursday, August 20, 2026

L
Leila Rashidi 12:46 PM
When will have first scale up rack with optics in industry?
1 reply
A
acalduino 1:37 PM
It's likely we'll see early product implementations in 2027
H
Hank Lee 12:47 PM
The OCI MSA 1.0 announced this year supports 200Gbps/fiber/direction.
Is there a possibility of evolving to 400Gbps/fiber/direction in the future?
If so, are there any architectures currently being considered?
1 reply
A
acalduino 1:39 PM
As we shared in the talk (slide 5), we are targeting a GEN2 / 400G spec in 2027. We'll share more details on architecture at a later date.
T
Taylor Groves 12:48 PM
Thanks for the talk Drew, what do you see as the key technical decisions that remain on Gen 1 and Gen 2 link architectures?
3 replies
T
Taylor Groves 1:00 PM
In reference to the "yarn ball" you showed. Anything stand out as a top priority or concern?
A
acalduino 1:40 PM
GEN1 is completed. GEN2 architectures are still being considered.
A
acalduino 1:41 PM
re: yarn ball - there are many categories here, and they're all evolving, power efficient, manufacturable BW scaling is the #1 challenge and goal
✅ 1
L
Leila Rashidi 1:11 PM
Is it possible to use CPO for XPU? It was not mentioned in usecases?
A
Ahmed Khalil (unaffiliated) 1:16 PM
One thing that jumped out was the deskew and relink timing table being in the hundreds of milliseconds. Is “low latency” here mainly steady-state link latency, and will OCI eventually define a tighter bounded-recovery target for a link flap?
1 reply
A
acalduino 2:41 PM
Link initialization, which is what is captured with deskew and relink timing, is very different than a link flap. It is unlikely that OCI MSA will define/bound the "link flap" time as it is dependent on each user and training workload.
C
Cissy Yuan 1:17 PM
@Rang-Chen Yu Impressive talk! Great to know so many options available to innovate system architecture. What's the relationship of open CPX and OCI?
1 reply
R
Rang-Chen Yu 1:45 PM
Hi Cissy: As I discussed on last page of Roadmap, CPX defines socket and form factor, OCI is Optical PMD. So CPX optics can support OCI as a viriant of Open CPX type.
B
bsahu 1:18 PM
What are the advanced packaging technologies used in Diablo 1 6.4T optical engines?
C
Chris Browning (Black Semi) 1:18 PM
CPX is a connector / formfactor. OCI is an optical / optical PHY standard. OCI would go in a CPX
T
Taylor Groves 1:20 PM
Thanks Ryan, on the CPX roadmap slide how will OpenCPX support different link architectures and physical dimensions (e.g. 400G to OCI gearbox on the top right). Will there be more classifications beyond Type 1/2, ELS/ILS in the future?
1 reply
R
Rang-Chen Yu 1:47 PM
We defined 1st release spec. for 32x200G-DR optics. There will be more variants coming up as part of OpenCPX project.
✅ 1
A
andrewliang823 1:20 PM
MCF benifit cw+siph more or vcsel array too?
L
Leila Rashidi 1:21 PM
Can't MCF be used for scale up?
C
Cissy Yuan 1:22 PM
@Gabe Sudduth MCF is on-chip or on-die since chips are all multi-core already?
1 reply
R
Rang-Chen Yu 1:54 PM
As part of SDM4 MCF MSA founding member, We have demonstrated MCF native 800G and 1.6T optical transceivers with interface from TRx to MCF.
K
Kapil Shrikhande 1:22 PM
Thanks Ryan, great talk - showing how Open CPX can provide the full range of optical / copper , XPU / Switch, CPO / NPO connectivity.
1 reply
R
Rang-Chen Yu 1:48 PM
That's our mission to provide widest choice and options for end customer deployment.
N
nicky 1:29 PM
Thank you that was really insightful,, is the long-term vision essentially to have standardised optical links like OCI on one side, but increasingly integrated PIC interfaces like GlassBridge on the other ?
H
Hank Lee 1:36 PM
I like both your talks yesterday and today.
Can XPO be companied with LPO, instead of LRO? If yes, what do you expect the energy effiency would be? (XPO LRO was 10pJ/b yesterday)
2 replies
R
Rang-Chen Yu 1:50 PM
XPO supports LPO, RTLR (LRO), and FRO (fully retimed). LPO power efficiency ~ 6pj/b
S
Sayan Ghosh 1:52 PM
@spriyadarshi
G
Gabe Sudduth 1:42 PM
On MCF, scale up solutions are under review (whether SiPh or vcsel) by many in industry. Several factors to address there that are different than scale out, inc. factoring how cores need to connect to all other gpus in the rack or pod
A
Ahmed Khalil (unaffiliated) 1:43 PM
@Gabe Sudduth The 4x density is compelling. One thing I’m wondering: does putting four cores in one cladding also turn one dirty connector, bad splice or marginal bend into a four-channel fault? Will the spec define core mapping and per-core pass/fail tests all the way through installation?
S
spriyadarshi 1:48 PM
hi
L
Leila Rashidi 1:57 PM
Does Qualcomm have optical scale up in their roadmap?
1 reply
T
Taylor Groves 1:58 PM
You want to put this in :#C0BQYJA3WTX