Tuesday, August 18, 2026
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Thursday, August 20, 2026
N
Thank you very informative talk,, in your co optimization flow is the optimal design set agnostic to the high-speed trace characteristics of the underlying substrate, or does the genetic algorithm need to co-simulate the exact substrate impedance mismatch and reflections to allow the DSP equaliser to find its true global optimum? I assume its the second which makes me think that glass substrates will bring about a great challenge?
1 reply
D
Hi Nicky, these are great questions. First, I want to note that the GA will only find a fairly good solution, and not necessarily the global optimum. For the point on substrates, the algorithm is needs substrate specific data -- definitely not substrate-agnostic. The specific transmission line in our example was simulated using Ansys HFSS to gather the relevant inputs.
L
Does Qualcomm have optical scale up in their roadmap?
1 reply
D
Hi Leila - yes, I have optical scale up in my roadmap.
T
For latency-sensitive AI interconnects, do coherent optics and its DSP introduce meaningful latency? If so, how do you trade off their benefits against the additional processing latency?
1 reply
D
Hi Tong, this is an interesting question! Yes, the DSP can introduce meaningful latency to the overall analysis. If a link can be accomplished with unretimed copper, but with anything more complicated... it's important to look at the overall end-to-end latency.
Using optical may allow for reduced or even the elimination of retimers and potential switching stages. CPO allows for the best latency performance among CPO, NPO, LPO options.
Similar to my point on copper vs optical, I would utilize the simplest optical/DSP architecture that satisfies your reach and link margin requirements. Coherent DSP make sense when other tools are insufficient, and using Coherent allows for an overall reduction in link latency/power.
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A
That narrow-line result with the 16-tap DSP was a great co-design example. Did the optimizer include PVT/package variation and equalizer power and noise, or was it mainly targeting the nominal transfer response? Curious how you stop the ML/GA from finding a fast but fragile corner.
1 reply
D
Hi Ahmed, thanks for compliment!
To your point, the design is optimizing for a nominal design point, not the full set of corner variations or Monte Carlo analyses. It's always a danger of blind optimization to hit a high-FOM yet fragile corner.
For the nominal search in the GA, one can add explicit penalties for power, noise, sensitivity, tap count, etc. These models are flexible and it's an art to find the parameters that matter most -- trading off run time vs near-optimal solution goals.
Regardless of serial or parallel candidates, the final signoff should run a complete coupled analysis over all practical variations to be covered.
Practically, I like to take several candidates across corner variation before making a decision.
A
On co-design practicalities say if the DSP, package stack-up or photonic engine changes late, can you tell which analyses need to be rerun, or does the whole optimization and signoff loop effectively start over?