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Technical Paper Session A: Network Hardware

August 17 @ 11:10 am - 12:00 pm UTC-7

11:10 – 11:30: Highly Integrated 4 Tbps Silicon Photonic IC for Compute Fabric Connectivity
Authors:
Saeed Fathololoumi, Christian Malouin, David Hui, Kadhair Al-Hemyari, Kimchau Nguyen, Pegah Seddighian, Yen-Jung Chen, Ye Wang, Aidong Yan, Reece Defrees, Thomas Liljeberg and Ling Liao

In this work we present the design and performance of a high bandwidth, low power, and high-density Silicon Photonic integrated circuit (SiPIC) for compute interconnects. The SiPIC has more than 4 Tbps bandwidth over eight standard single mode fiber pairs. Each fiber pair carries eight DWDM transmit and receive channels operating at 32 Gbps NRZ. We integrate all photonic components and functions including lasers, semiconductor optical amplifiers (SOAs), modulators, photodetectors, spot size convertors and V-grooves onto a single silicon die. Device design and performance details are discussed.

11:30 – 12:00: Compute Express Link®: An open industry-standard interconnect enabling heterogenous data-centric computing
Authors: Debendra Das Sharma

Compute Express Link is an open industry standard interconnect offering caching and memory semantics on top of PCI Express. In addition to providing high-bandwidth and low-latency connectivity between host processor and accelerators, smart network interface card, and memory expansion devices, it also enables resource pooling across multiple systems for scalable, power-efficient and cost-effective computing. This paper delves into the micro-architectural design to deliver power-efficient performance based on our experience designing a Xeon CPU and FPGA with this technology with demonstrated silicon interoperability. We also discuss new architectures to enable pooled memory and accelerators for reducing the total cost of ownership while delivering power-efficient performance with CXL.