Call for Papers
Topics of Interests
- Novel and innovative interconnect architectures
- Accelerator interconnects, e.g. NVLINK, Infinity Fabric
- Network software/hardware designed for AI/ML workloads
- Multi-core processor interconnects
- System-on-Chip Interconnects
- Chiplet-interconnect technologies such as UCIe and BOW
- Advanced chip-to-chip communication technologies
- Optical interconnects
- Protocol and interfaces for inter-processor communication
- Survivability and fault-tolerance of inter-connects
- High-speed packet processing engines and network processors
- Systems software for communication
- System and storage area network architectures and protocols
- High-performance host-network interface architectures
- High-bandwidth and low-latency I/O
- Pb/s switching and routing technologies
- Innovative architectures for supporting collective communication
- Novel communication architectures to support cloud & grid computing
- Centralized and distributed cloud interconnects
- Requirements driving high-performance interconnects
- Traffic characterization for HPC systems and commercial data centers
- Software-defined networking and software overlay networks
- Software for network bring-up, configuration and performance management (OpenFlow, OpenSM)
- Data Center Networking
Submissions and Schedule
- Paper abstract deadline:
May 13, 2024May 27, 2024 - Submission deadline: May 27, 2024
- Notification of acceptance:
June 22, 2024June 28, 2024 AOE
2024 Conference Theme -
Can Interconnects Keep up with AI?
The explosion of AI and workloads related to machine learning and deep learning boggles the mind. Whether in massive data centers, edge locations, automobiles, or consumer appliances, AI stands to improve many tasks useful to people at work or at leisure. The demand for GPUs, DPUs, TPUs, and IPUs taxes the ability of their manufacturers to meet the market demand. Efficient utilization of these xPUs requires high speed and highly scalable interconnects. Whether between xPUs or between an xPU and memory, data transfer can easily become a bottleneck in computing efficiency.
In this edition of IEEE Hot Interconnects, we explore advances in interconnection networks that alleviate this bottleneck. Solutions including optical circuit switching, dense photonic data paths, high-performance fabrics, and more will expand from the specialized applications of HPC to the pervasive applications of AI and in the process will become more affordable. This year’s HotI will thus be captivatingly relevant.
Paper Format
This year we invite papers to be submitted either as regular, long papers (6-8 pages) or as hot topic papers (3-4 pages). Hot topic papers could be positional papers, industry papers, or papers describing hot-off-the-press breaking research results, and will be judged accordingly and independently from the regular long papers.
- Papers need sufficient technical detail to judge quality and suitability for presentation. Submissions must conform to [IEEE ethics standards].
- Submissions should include title, author, abstract, and paper in double-column, see [IEEE format] for details.
- Regular/Long paper limit: 6-8 pages, single-spaced, 2 columns, excluding references.
- Hot topic paper limit: 3-4 pages, single-spaced, 2 columns, including references.
- Accepted papers (both long and hot topic papers) will be published in IEEE Xplore Digital Library. We plan to invite the best papers for an [IEEE Micro] Special issue submission.
- Papers should be submitted electronically through [EasyChair].
Safety and Well-being
Given the success of previous year’s online format, Hot Interconnects 2024 will continue to be an online conference.