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Standardizing Interconnect Test and Repair: Motivation and On-Going Effort
Title: Standardizing Interconnect Test and Repair: Motivation and On-Going Effort
Abstract:
Chip-let based design, fueled by various advanced packaging technologies, is projected to revolutionize the semiconductor industry. This brings along with it associated challenges to achieve adequate yield and contain aging related reliability issues. This talk will present manufacturing defect profiles associated with advanced packaging; the test and repair requirement, during high volume manufacturing, to achieve adequate yield; and challenges associated with latent defects leading to aging related field failures. The talk concludes by highlighting IEEE P3405, an ongoing effort to standardize chip-let interconnect test and repair to enable chip-let based Lego-like design.
Speaker Biography:
Dr. Sreejit Chakravarty is an IEEE Fellow, a highly recognized Researcher, Inventor, and a Distinguished Engineering Leader, with extensive industry and academic experience.
He is currently a Distinguished Engineer at Ampere Computing, Santa Clara, CA, USA where he drives the strategic initiatives for product quality. Prior to this he had over 25 years of industry experience as a Principal Engineer with Intel Corporation and Distinguished Engineer at LSI and AVAGO (now Broadcom). He started his career in academia as an Associate professor of Computer Science, at The State University of New York at Buffalo, where his work was funded by multiple National Science Foundation Grants.
He has architected innovative solutions across the entire silicon life cycle spanning Silicon Quality and Reliability (RAS, Functional Safety and Silent Data Errors); and subsequently drove them from concept to product intercept.
He has published 1 book, authored 145+ IEEE papers and has 23 issued US patents. He has served in various capacity at numerous IEEE conferences and delivered multiple keynote addresses, the latest being at the IEEE Asina Test Symposium, 2023. He has mentored research at several universities like Princeton, USC, UIUC, etc. For his professional work he has been recognized as an IEEE Fellow and SUNY Distinguished Alumni. He currently chairs the IEEE P3405 Work Group on Chip-let Interconnect Test and Repair, which aims to standardize the test and repair of chip-let interconnects which will lay the foundation to realize the chip-let revolution.