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Technical Paper Session A: Interconnect Standards

August 23 @ 9:15 am - 10:15 am UTC-7

Technical Paper Session A: Interconnect Standards

Session Chair: Scott Levy (Sandia National Laboratory)

Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express® 6.0

Authors: Debendra Das Sharma and Swadesh Choudhary (Intel).

Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express® 6.0.PCI Express® (PCIe®) specification has been doubling the data rate every generation in a backward compatible manner every three years. PCIe 6.0 specification will adopt PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach, cost, and power profile as prior generations. A Forward Error Correction (FEC) mechanism will offset the high BER of PAM-4. A strong Cyclic Redundancy Check (CRC) and a link level replay mechanism will deliver a low-latency, high bandwidth efficiency, and highly reliable solution expected of a Load-Store interconnect. We propose a non-pipelined implementation of the FEC and CRC that is part of the PCIe 6.0 base specification. We also propose a partitionable and pipelined implementation for FEC and CRC for lowering gate count and latency. We have tested the correctness of our register transfer logic (RTL) implementation in a field programmable gate array (FPGA) implementation along in addition to simulation. Synthesis results from Synopsys DC compiler demonstrates that for a x16 PCIe Link partitionable to up to x4s, with 4 independent controller using independently partitionable logic, we achieve a gate count of about 100,000 for the transmit and receive side with a FEC + CRC delay of less than 1 nsec in each direction.

Level 4 Autonomous Driving SoC, leveraging chiplet, advanced package and UCIe

Authors: Vinayak Agrawal (Intel), Francios Piednoel (Mercedes-Benz), Igor Elkanovich (Global Unichip), Mirza Jahan (Intel) and Sil Dwaipayan (Intel)

Abstract: With the unprecedented growth of High-Performance Compute (HPC) and Autonomous Driving (AD) seen in recent times, the traditional chip design strategy is falling short and encountering a fundamental manufacturing limit. Smaller silicon dice, or “chiplets,” combined in a single package, with aggregate silicon area much greater than a reticle, are becoming popular and showing great promise to effectively mitigate the yield and size challenges of the traditional approach. While chiplets solve some problems, they introduce new challenges of interoperability, higher interconnect power and latency, and the availability of a chiplet to chiplet IO that can meet bandwidth and reliability requirements. In this paper, we will demonstrate how heterogenous chiplets sourced from different vendors, and designed in diverse nodes, can leverage the UCIeTM interconnect standard, along with advanced packaging, to unleash unprecedented interconnect density, bandwidth, and automotive grade reliability with best-in-class power to pave the path for building a leading Level 4 AD product.