Click here to REGISTER or JOIN the event!

Program

All times are in UTC -7 (America/Los_Angeles)

Day 1 (Aug, 21st)

Day 2 (Aug, 22nd)

Day 3 (Aug, 23rd)

Day 1 (Aug, 21st)

Time (UTC-7)	Title
08:50	Introduction and Welcome Session Chair: Matthew Dosanjh
09:00	Technical Paper Session A: Networks for Large Language Models Session Chair: Shelby Lockhart (AMD) Rail-only: A Low-Cost High-Performance Network for Training LLMs with Trillion Parameters Weiyang Wang, Manya Ghobadi, Kayvon Shakeri, Ying Zhang and Naader Hasani [SLIDES] Characterizing Communication in Distributed Parameter-Efficient-Fine-Tuning for Large Language Models Nawras Alnaasan, Horng-Ruey Huang, Aamir Shafi, Hari Subramoni and Dhabaleswar K. Panda [SLIDES]
10:00	Keynote: Keeping Pace: Micro-Models, Large Language Models, and the Co-Evolution of Chip and Data Center Design in a Rapidly Shifting AI Landscape Speaker: Mark Baciak (CTO, NeuralFabric)
11:00	Platinum Sponsor Talk: Universal Memory Interface (UMI): A practical solution to break the memory wall for AI ASICs Speaker: Ramin Farjadrad (Co-Founder and CEO, Eliyan) [SLIDES]
11:15	Break
11:25	Technical Paper Session B: Interconnection Network Session Chair: Xiaoyi Lu (UC Merced) Quality-of-Service Provision for BXI3-based Interconnection Networks Miguel Sánchez de la Rosa, Gabriel Gabriel Gomez-Lopez, Francisco J. Andújar, Jesús Escudero-Sahuquillo, José L. Sánchez, Francisco J. Alfaro and Pierre-Axel Lagadec [SLIDES] A new Mechanism to Identify Congesting Packets in High-Performance Interconnection Networks [BEST ACADEMIC PAPER AWARD] Cristina Olmedilla, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles, Wenhao Sun, Long Yan, Yunping Lyu and Jose Duato [SLIDES]
12:15	Lunch
13:00	Keynote: Connectivity for AI Everywhere: The Role of Chiplets Speaker: Tony Chan Carusone (CTO, Alphawave semi) [SLIDES]
14:00	Panel: Bandwidth Scaling for AI Interconnect – More Wavelengths vs More Fiber? Moderator: Dr. Katharine Schmidtke Panelists: Dr. Dan Kuchta (IBM Research) [SLIDES], Dr. Peter Winzer (Nubis Communications) [SLIDE], Dr. Rebecca Schaevitz (MixxTech, Inc) [SLIDES], Dr. Amit Nagra (Intel), Dr. Alan Liu (Quintessent Inc.) [SLIDES], Dr. Bardia Pezeshki (Avicena Tech) [SLIDES]
15:30	The Head Bubba Memorial and HOTI Closing Remarks Day 1 Speaker: Dan Pitt

Day 2 (Aug, 22nd)

Time (UTC-7)	Title
09:00	Day 2 Welcome
09:10	Technical Paper Session C: Collectives for Deep Learning Session Chair: Amanda Bienz (UNM) Towards a Standardized Representation for Deep Learning Collective Algorithms Jinsun Yoo, William Won, Meghan Cowan, Nan Jiang, Benjamin Klenk, Srinivas Sridharan and Tushar Krishna [SLIDES] Unified Collective Communication (UCC): An Unified Library for CPU, GPU, and DPU Collectives [BEST INDUSTRY PAPER AWARD] Ferrol Aderholdt, Manjunath Gorentla Venkata, Valentine Petrov, Sergey Lebedev, Devendar Bureddy, Joshua Ladd, Gil Bloch, Mike Dubman and Gilad Shainer [SLIDES]
10:00	Keynote: Powering Llama 3: A Sneak-peek into Meta’s Massive Infrastructure for Generative AI Speaker: Pavan Balaji (Meta)
11:00	Gold Sponsor Talks Arista GigaIO [SLIDES]
11:20	Break
11:30	Invited Talk: “Can Interconnects Keep up with AI? YES .” Speaker: Andy Bechtolsheim (Arista) [SLIDES]
12:00	Lunch
13:00	Technical Paper Session D: Optimizing Collective Operations Session Chair: Craig Stunkel (Nvidia) OHIO: Improving RDMA Network Scalability in MPI_Alltoall through Optimized Hierarchical and Intra/Inter-Node Communication Overlap Design Tu Tran, Goutham Kalikrishna Reddy Kuncham, Bharath Ramesh, Shulei Xu, Hari Subramoni, Mustafa Abduljabbar and Dhabaleswar K. Panda [SLIDES] Demystifying the Communication Characteristics for Distributed Transformer Models Quentin Anthony, Benjamin Michalowicz, Jacob Hatef, Lang Xu, Mustafa Abduljabbar, Aamir Shafi, Hari Subramoni and Dhabaleswar Panda [SLIDES]
14:00	Sponsor Videos Nutanix [VIDEO] [SLIDES] Lenovo
14:10	Break
14:20	Invited Talk: Standardizing Interconnect Test and Repair: Motivation and On-Going Effort Speaker: Sreejit Chakraverty (Ampere Computing) [SLIDES]
14:50	Invited Talk: Ultra Ethernet Consortium (UEC) overview – solving the AI/HPC Scale-Out Network Challenge Speaker: Uri Elzur (Intel)
15:15	HOTI Closing Remarks Session Chair: Artem Polyakov

Day 3 (Aug, 23rd)

Track 1 Session Chair: David Ozog (Intel)
Time (UTC-7)	Title
08:00	Linear Electro-Optical Interface: Standardization, Design Principles & Silicon Correlation Priyank Shukla and Ruben Sousa (Synopsys)
10:00	OFI Libfabric, APIs for MPI & CCL Rajalaxmi Angadi, Juee Himalbhai Desai, and Peinan Zhang (Intel)
11:30	Lunch
12:30	Chip-let Interconnect Test and Repair Sreejit Chakravarty
15:00	ASTRA-sim and Chakra: Enabling Software-Hardware Co-design Exploration for Distributed Machine Learning Platforms Tushar Krishna and William Won (Georgia Tech)
Track 2 Session Chair: Amanda Bienz (UNM)
Time	Title
08:00	High-Performance and Smart Networking Technologies for HPC and AI Dhabaleswar K. (DK) Panda and Hari Subramoni
10:45	Short Break
11:00	Leveraging SmartNICs for HPC and Data Center Applications Jeffrey Young, Rich Graham, Oscar Hernandez, Antonio Peña, Sergio Iserte, and Richard Vuduc
13:45	Short Break
14:00	Principles and Practice of Scalable and Distributed Deep Neural Networks Training and Inference Dhabaleswar K. (DK) Panda, Hari Subramoni, Aamir Shafi, and Nawras Alnaasan